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mitsubishi lsis may.1998 , rev.1.2 16777216-bit (2097152-word by 8-bit) cmos 3.3v-only flash memory & 2097152-bit (262144-word by 8-bit) cmos static ram stacked-mcp (multi chip package) M6MF16S2AVP preliminary notice : this is not a final specification. some parametric limits are subject to change. 1 description the mitsubishi M6MF16S2AVP is a stacked muti chip package (s-mcp) that contents 16m-bit flash memory and 2m-bit static ram in a 48-pin tsop (type-i). 16m-bit flash memory is a 2097152 bytes, 3.3v-only, and high performance non-volatile memory fabricated by cmos technology for the peripheral circuit and dinor(divided bit-line nor) architecture for the memory cell. 2m-bit sram is a 262144 bytes unsynchronous sram fabricated by silicon-gate cmos technology. M6MF16S2AVP is suitable for the application of the mobile-communication-system to reduce both the mount space and weight . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a20 a19 a18 a16 a15 a14 a13 s-we# s-ce2 a12 f-ce# f-vcc s-vcc f-rp# a11 a10 a9 a8 a7 a6 a5 a4 nc f-wp1# s-oe# a17 f-we# f-oe# s-ce1# dq7 dq6 dq5 dq4 f-vcc f-gnd f-gnd dq3 s-gnd dq2 dq1 dq0 a0 a1 a2 a3 nc 14.0 mm f-wp2# pin configuration (top view) f-vcc :vcc for flash f-gnd :gnd for flash s-vcc :vcc for sram s-gnd :gnd for sram a0-a17 :flash/sram common address a18-a20 :address for flash f-ce# :flash chip enable f-we# :flash write enable dq0-dq7 :data i/o f-wp1#,wp2# :flash write protect f-rp# :flash reset power down s-ce1#,ce2 :sram chip enable s-we# :sram write enable s-oe# :sram output enable f-ry/by# :flash ready /busy f-oe# :flash output enable nc:non connection f-ry/by# 10.0 mm ?access time (flash memory, sram) 110ns (max.) ?supply voltage vcc=2.7 ~ 3.6v ?ambient temperature ta=-20 ~ 85? ?package : 48-pin tsop (type-i) , 0.4mm lead pitch application features mobile communication products
mitsubishi lsis may.1998 , rev.1.2 16777216-bit (2097152-word by 8-bit) cmos 3.3v-only flash memory & 2097152-bit (262144-word by 8-bit) cmos static ram stacked-mcp (multi chip package) M6MF16S2AVP preliminary notice : this is not a final specification. some parametric limits are subject to change. 2 block diagram dq 0 dq 1 dq 2 dq 3 s-v cc s-gnd (0v) s-we# s-oe# dq 4 dq 5 dq 6 dq 7 s-ce1# address input buffer row decoder 262144 words x 8 bits (512 rows x 128columns x 32 blocks) clock generator sense amp. output buffer a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 0 a 1 a 2 a 13 a 14 a 15 a 16 a 17 a 3 s-ce2 address input buffer data input buffer data inputs/outputs (in common to flash memory) a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 f-ce# f-oe# f-we# f-v cc f-gnd (0v) dq 0 dq 1 dq 2 dq 3 dq 5 dq 6 dq 7 dq 4 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 f-wp1#,wp2# f-rp# reset/power down input f-ry/by# ready/busy output multiplexer command user interface write state machine status / id register 256 byte page buffer 64k byte block0 64k byte block1 64k byte block2 64k byte block31 x-decoder y-decoder y-gate / sense amp. input/output buffers address inputs (a0-a17 is in common to sram) chip enable input write enable input data inputs/outputs (in common to sram) write protect input 16m flash memory 2m sram address inputs (in common to flash memory) output enable input column decoder address input buffer block decoder
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 1. flash memory 3 function the flash memory of M6MF16S2AVP includes on-chip program/erase control circuitry. the write state machine (wsm) controls block erase, page (256byte) program operations. operational modes are selected by the commands written to the command user interface (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. a deep powerdown mode is enabled when the rp# pin is at gnd, minimizing power consumption. read the flash memory of M6MF16S2AVP has three read modes, which accesses to the memory array, the device identifier and the status register. the appropriate read command are required to be written to the cui. upon initial device powerup or after exit from deep powerdown, the flash memory automatically resets to read array mode. in the read array mode, low level input to ce# and oe#, high level input to we# and rp#, and address signals to the address inputs (a0-a20) output the data of the addressed location to the data input/output(d0-d7). write writes to the cui enable reading of memory array data, device identifiers and reading and clearing of the status register. they also enable block erase and program. the cui is written by bringing we# to low level, while ce# is at low level and oe# is at high level. addresses and data are latched on the earlier rising edge of we# and ce#. standard micro-processor write timings are used. output disable when oe# is at vih, output from the devices is disabled. data input/output are in a high-impedance(high-z) state. standby when ce# is at vih, the device is in the standby mode and its power consumption is reduced. data input/output are in a high-impedance(high-z) state. if the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. deep power-down when rp# is at vil, the device is in the deep powerdown mode and its power consumption is substantially low. during read modes, the memory is deselected and the data input/output are in a high-impedance(high-z) state. after return from powerdown, the cui is reset to read array , and the status register is cleared to value 80h. during block erase or program modes, rp# low will abort either operation. memory array data of the block being altered become invalid. software command definitions the device operations are selected by writing specific software command into the cui. read array command (ffh) the device is in read array mode on initial device powerup and after exit from deep powerdown, or by writing ffh to the cui. the device remains in read array mode until the other commands are written. read device identifier command (90h) the device identifier is read after writing the read device identifier command of 90h to the command user interface. following the command write, the manufacturer code and the device code can be read from address 000000h and 000001h, respectively. read status register command (70h) the status register is read after writing the read status register command of 70h to the command user interface. the contents of status register are latched on the later falling edge of oe# or ce#. so ce# or oe# must be toggled every status read. clear status register command (50h) the erase status and program status bits are set to "1"s by the write state machine and can be reset by the clear status register command of 50h. these bits indicates various failure conditions. block erase / confirm command (20h/d0h) automated block erase is initiated by writing the block erase command of 20h followed by the confirm command of d0h. an address within the block to be erased is required. the wsm executes iterative erase pulse application and erase verify operation. suspend/resume command (b0h/d0h) writing the suspend command of b0h during block erase operation interrupts the block erase operation and allows read out from another block of memory. writing the suspend command of b0h during program operation interrupts the program operation and allows read out from another block of memory. the device continues to output status register data when read, after the suspend command is written to it. polling the wsm status and suspend status bits will determine when the erase operation or program operation has been suspended. at this point, writing of the read array command to the cui enables reading data from blocks other than that which is suspended. when the resume command of d0h is written to the cui, the wsm will continue with the erase or program processes.
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 4 data protection the flash memory of M6MF16S2AVP provides hardware-locking of memory blocks. each block has an associated nonvolatile lock-bit which determines the lock status of the block.in addition, this flash memory has a master write protect pin (wp) which prevents any modifications to memory blocks. when wp2# is at low, all memory blocks are locked. and when both wp1# and wp2# are at low, this part is in read array only mode.(not be accepted any write command) when wp1# is at low and wp2# is at high, the memory blocks whose lock-bits are set to "0" are locked. when both wp1# and wp2# are at high, lock-bits can be programmed (to "0"), all blocks can be programmed or erased regardless of the state of the lock-bits, and lock-bits are cleared to "1" by this erase. see the block locking table on p.6 for details. power supply voltage when the power supply voltage (vcc) is less than 2.2v, the device is set to the read-only mode. a delay time of 2 us is required before any device operation is initiated. the delay time is measured from the time vcc reaches vccmin. during power up, f-rp#=gnd is recommended. falling in busy status is not recommended for possibility of damaging the device. program command program consists of data load sequence to page buffer and data program sequence to flash memory array. a) start load page buffer (dbh/xxh/xxh) writing start load page buffer command allows data load to page buffer. dbh is written to the cui, follwed by two write cyclle of a certain command except for block erase command(20h/d0h) and lock bit program command(77h/d0h). b) sequential load to page buffer (dbh/ffh/00h) writing sequential load to page buffer command allows 256 bytes data load to page buffer sequentially. follwing a three - command sequence(dbh/ffh/00h) , 256 writes cycle specifying the address and data executes loading to page buffer. in this mode, only a0-7 is used and a8-a20 is a don't care. c) end load page buffer (5fh/xxh/xxh) writing end load page buffer command ends data load to page buffer. 5fh is written to the cui, follwed by two write cyclle of a certain command except for block erase command(20h/d0h) and lock bit program command(77h/d0h). the data of page command is stored while vcc power is on or until writing page buffer write to flash command or page buffer clear command.the stored data in page buffer can be changed by data load sequence follwed by re-start load page buffer. d) page buffer write to flash (0eh/d0h) programming to flash memory array from page buffer is executed by page buffer write to flash command. the page buffer write to flash setup command (0eh) is witten to the cui, followed by the confirm commasnd (d0h). in this mode, a8-a20 is used. the wsm controls the program pulse application and verify operation. after programming, each page buffer is cleared to "ffh". and the page buffer data is invaid in the suspend mode. basically re-program must not be done on a page which has already programmed.
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 5 memory map 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block 32kword block flash memory memory map a 0 - a 20 060000h-06ffffh 050000h-05ffffh 040000h-04ffffh 030000h-03ffffh 020000h-02ffffh 010000h-01ffffh 000000h-00ffffh 1f0000h-1fffffh 1e0000h-1effffh 1d0000h-1dffffh 1c0000h-1cffffh 1b0000h-1bffffh 1a0000h-1affffh 190000h-19ffffh bus operations 1) f-ce# f-oe# f-we# dq 0-7 v il v il v il v il v ih v il v il v il v il v il v ih x v ih v ih v ih v ih v ih v ih x v il v il f-rp# v ih v ih v ih v ih v ih v ih v ih f-ry/by# x x x x x x v il v ih x v il x v ih v il x 2) v il v il v ih v ih x v oh(hi - z) v oh(hi - z) v oh(hi - z) mode array status register identifier code stand by program erase write read pins output disable deep power down others lock bit status data out status register data identifier code hi-z hi-z command/data in command hi-z command lock bit data (dq 6 ) 1) x at ry/by# is v ol or v oh(hi-z) . *the ry/by# is an open drain output pin and indicates status of the internal wsm. when low,it indicates that the wsm is busy performing an operation. a pull-up resistor of 10k-100k ohms is required to allow the ry/by# signal to transition high indicating a ready wsm condition. 2) x can be v ih or v il for control pins.
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 6 block locking 1) when the lock bit is "0" ,its block cannot be programed and erased. lock bit is set to "0" by lock bit program. locked bit("0") is cleared to "1" with block memory by block erase on setting unlock mode. 2) dq 6 provides lock bit status of each block after writing the read lock status command (71h). 3) wp# pin must not be switched during performing read / write operations or wsm busy (wsms = 0). 4) the device prpvides a complete read array only mode. (not be accepted any write command, including read mode command, ex:device identifier, read status register.) 5) x can be v ih or v il for control pins. all blocks/lock bits locked (deep power down mode) all blocks/lock bits unlocked (erase/program enable) rp# wp2# v il v hh v ih erase/program operation x x v il v ih unlock unlock lock write protection provided memory block unlock unlock lock wp1# v ih x x v il v il v ih lock lock alll blocks/lock bits locked (read array only mode) 1) all blocks/lock bits locked locked by lock bit lock bit depend on lock bit data 4) software command definition status register data (srd) status erase status program status definition symbol (d 5 ) (d 4 ) write state machine status (d 7 ) suspend status (d 6 ) reserved device sleep status (d 1 ) (d 0 ) block status after program (d 3 ) reserved (d 2 ) "1" "0" ready busy suspended operation in progress / completed error successful error successful - - - - device in sleep device not in sleep *dq3 indicates the block status after the page programming. when dq3 is "1", the page has the over-programed cell . if over-program occurs, the device is block fail. however if dq3 is "1", please try the block erase to the block. the block may revive. sr.5 sr.4 sr.7 sr.6 sr.1 sr.0 sr.3 sr.2 error successful read array ffh x 1) ia=id code address : a 0 =v il (manufacture's code) : a 0 =v ih (device code), id=id code, a 1 -a 20 =v il 2) srd=status register data 3) ba=block address (a 16 -a 20 ) 4) two dummy write cycle is necessary,except for block erase/confirm command(20h/d0h) and lock bit program/confirm command(77h/d0h), after start page buffer load command and end load page buffer command. 6) wa=write address : page buffer data is programmed to the same page address in the memory arrary, and address a0-7 is ignored. 7) dq6 provides block lock bit status, dq6=1 : block unlock , dq6=0 : block locked. 8) sleep command (f0h) put the device into the sleep mode after completing the current operation. the active current is reduced to deep power -down levels. the read array command (ffh) must be written to get the device out of sleep mode. device identifier 90h x id ia read status register 70h x srd x clear status register 50h x block erase / confirm 20h x d0h ba suspend b0h x resume d0h x 1) 1) 2) 3) command data address read ist bus cycle mode 1st bus cycle data address mode data address mode read write write page buffer write to flash 0eh x d0h wa read lock bit status 71h x lock bit program / confirm 77h x 6) erase all unlocked blocks / confirm a7h x d0h x sleep f0h x 8) d 6 ba d0h ba 7) write read write write sequential load page buffer e0h x ffh x 00h x 5) write write start load page buffer dbh x x x write write x x end load page buffer 5fh x x x write write x x 4) 2nd bus cycle 3rd bus cycle write write write write write write write write write write write write write write lock lock lock all blocks/lock bits unlocked (erase/program enable)
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. conditions parameter with respect to ground symbol f-v cc all input or output voltage except for vcc,rp# v i1 vcc voltage (flash memory) 1) unit v v min. ambient temperature temperature under bias t a t bs storage temperature t stg ? ? ? output short circuit current i out ma v i2 rp# supply voltage v absolute maximum ratings capacitance pf pf 8 12 ta = 25?, f=1mhz, v in =v out =0v c in c out symbol parameter test conditions unit max. typ. min. limits input capacitance (address, control pins) output capacitance note: the value of common pins to sram is the sum of flash memory and sram. device identifier code hex. data 1ch 69h d 0 0 1 a 0 v il v ih d 1 0 0 d 2 1 0 d 3 1 1 d 4 1 0 d 5 0 1 d 6 0 1 d 7 0 0 code manufacturer code device code pins dc electrical characteristics ( ta = -20 ~ 85?, vcc = 2.7v ~ 3.6v, unless otherwise noted ) symbol parameter test conditions vcc standby current i lo ?0 output leakage current ? 0v v out f-v cc i li input leakage current ? 0v v in f-v cc ?.0 vcc deep powerdown current output high voltage v v ol output low voltage v i ol = 4.0ma 0.45 vcc+0.5 v ih input high voltage v 2.0 0.8 v il input low voltage ?0.5 v oh1 i oh = ?.5ma 0.85vcc v v oh2 i oh = ?00? vcc?.4 v i cc3 vcc program currenrt ma 30 f-vcc = 3.6v, vin=vil/vih, f-ce# = f-rp# =f-wp1#,wp2# = vih i cc4 vcc erase current ma 40 v ihh 11.4 12.6 v rp# block unlock voltage 12.0 i rp rp# block unlock current f-rp# = v hh max 500 ? i cc5 vcc suspend current 200 ? i sb2 5 f-vcc=3.6v,vin=f-gnd or f-vcc, f-ce#=f-rp#=f-wp1#,wp2#=vcc 0.3v ? 0.1 25 ma i cc1 vcc read currenr f-v cc = 3.6v, v in =v il /v ih , f-ce# = v il , f-rp#=f-oe#=v ih , f = 5mhz, i out = 0ma 7 i sb1 f-vcc = 3.6v, vin=vil/vih, f-ce#=f-rp#=f-wp1#,wp2#=vih ? 200 50 i cc2 30 ma f-vcc=3.6v,vin=vil/vih,f-ce#=f-we#=vil,f-rp#=f-oe#=vih f-v cc = 3.6v, v in =v il /v ih , f-rp#= v il ? 15 5 i sb3 ? 5 0.1 i sb4 f-vcc = 3.6v, vin=f-gnd or f-vcc, f-rp#=f-gnd 0.3v vcc write current unit max typ min limits v lko low vcc lock-out voltage 2) 1.5 2.5 v 7 max. -0.2 4.6 -0.2 4.6 -0.6 14.0 -20 85 -30 85 -65 125 100 1) minimum dc voltage is -0.5v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.5v which, during transitions, may overshoot to v cc +1.5v for periods <20ns. all currents are in rms unless otherwise noted. 1) typical values at vcc=3.3v, ta=25? 2) to protect against initiation of write cycle during vcc power-up/ down, a write cycle is locked out for vcc less than v lko. if vcc is less than v lko, write state machine is reset to read mode. when the write state machine is in busy state, if vcc is less than v lko , the alteration of memory contents may occur. f-vcc = 3.6v, vin=vil/vih, f-ce# = f-rp# =f-wp1#,wp2# = vih f-vcc = 3.6v, vin=vil/vih, f-ce# = f-rp# =f-wp1#,wp2# = vih
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 8 read-only mode ac electrical characteristics ( ta = -20 ~ 85?, vcc = 2.7v ~ 3.6v, unless othe read/write mode (we# control) t rc t a (ad) t a (ce) t a (oe) t clz t olz t df(oe) t oh t oeh ns ns ns ns ns ns ns ns 110 30 0 110 110 110 55 0 0 t avav t avqv t elqv t glqv t elqx t glqx t ghqz t oh t whgl t ps ns 500 ns t phel max typ min read cycle time address access time chip enable access time output enable access time chip enable to output in low-z output enable to output in low-z output enable high to output in high z output hold from ce#, oe#, addresses oe# hold from we# high symbol parameter unit limits rp# high recovery to ce# low t df(ce) ns 30 t ehqz chip enable high to output in high z t phz ns 300 t plqz rp# low to output high-z t wc t as t ah t ds t dh t cs t ch chip enable hold time ns ns ns ns ns ns t wp t wph t dap t dae write pulse width write pulse width high duration of auto-program operation duraruin of auto-erase operation ns ns ns ms 110 t whrl write enable high to ry/by# low ns ms t avav t dvwh t whdx t elwl t wheh t wlwh t whwl t avwl t wlax t whrh1 t whrh2 10 50 10 50 60 0 0 50 5 20 110 t whrl t ps f-rp# high recovery to f-we# low ns 500 t phwl max typ min symbol parameter limits unit write cycle time address set-up time address hold time data set-up time data hold time chip enable set-up time t bls block lock set-up to write enable high t phhwh t wps ns 110 t blh block lock hold from valid srd t phhwh t wph ns 0 80 600 timing measurements are made under ac waveforms for read operations. read timing parameters during command write operations mode are the same as during read-only operations mode. typical values at vcc=3.3v, ta=25?
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. read/write mode (ce# control) erase and program performance block erase time block program time (page mode) page program time parameter ms sec ms unit 4 1.3 40 80 5 600 typ min max limits 9 vcc power up/down timing symbol 2 t vcs parameter rp# =v ih set-up time from vcc at 2.7v ? unit typ min max limits t wc t as t ah t ds t dh t ws t wh write enable hold time ns ns ns ns ns ns t cep t ceph t dap t dae ce# pulse width ce# pulse width high duration of auto-program operation duration of auto-erase operation ns ns ns ms 110 t ehrl chip enable high to ry/by# low ns ms t avav t dvwh t whdx t elwl t wheh t wlwh t whwl t avwl t wlax t whrh1 t whrh2 10 50 10 50 60 0 0 50 5 20 110 t ehrl t ps rp# high recovery to write enable low ns 500 t phwl max typ min symbol parameter limits unit write cycle time address set-up time address hold time data set-up time data hole time write enable set-up time t bls block lock set-up to write enable high t phhwh t wps ns 110 t blh block lock hold from valid srd t phhwh t wph ns 0 600 80 read timing parameters during command write operations mode are the same as during read-only operations mode. typical values at vcc=3.3v, ta=25? during power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. the device must be protected against initiation of write cycle for memory contents during power up/down. the delay time of min.2usec is always required before read operation or write operation is initiated from the time vcc reaches 2.7v during power up. by holding rp# v il , the contents of memory is protected during vcc power up/down. during power up, rp# must be held v il for min.2us from the time vcc reaches 2.7v. during power down, rp# must be held v il until vcc reaches gnd. rp# doesn't have latch mode ,so rp# must be held v ih during read operation or erase/program operation.
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 10 dut 3.3k w 1n914 1.3v c l input voltage test conditions for ac characteristics input rise and fall times (10%-90%) reference voltage at timing measurement cl vcc=2.7v ~ 3.6v 0v 3.0v 10ns 1.5v 100pf v il v ih test configuration output load : 1ttl gate + cl or capacitance load value vcc power up / down timing 3.3v gnd f-v cc v ih v il f-rp# read/write inhibit t vcs v ih v il f-ce# v ih v il f-we# t ps t ps read/write inhibit read/write inhibit ac waveforms for read operation and test conditions output valid high-z t df(oe) t rc v ih v il v ih v il v ih v il v ih v il v oh v ol addresses f-ce# f-oe# f-we# data address valid t oh t olz t a (ce) t oeh t clz t a (ad) t a (oe) high-z v ih v il f-rp# t ps t df(ce) t phz
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. ac waveforms for read/write (we# control) ac waveforms for read/write (ce# control) 11 note, (1) block rrase: din1=20h, din2=d0h ( t dae : duration of block erase) (2) page buffer write to flash : din1=0eh, din2=d0h ( t dap : duration of program) (3) lock bit program / confirm: din1=77h, din2=d0h ( t dap : duration of program) (4) erase all unlocked blocks / confirm : din1=a7h, din2=d0h ( t fers : duration of chip erase) din1 din2 t wph t wp t ds t dh t cs t ch t wc v ih v il v ih v il v ih v il v ih v il t ah v ih v oh v ol v il t as ffh srd t oeh t dap ,t dae t whrl prpgram or erase address valid t a(ce) t a(oe) read status register write read array command t ps v ih v il v ih v il f-ce# f-oe# f-we# f-ry/by# address data f-rp# f-wp1#, wp2# t wph t wps v hh t blh t bls din1 din2 t ds t dh t ws t wh t wc v ih v il v ih v il v ih v il v ih v il t ah v ih v oh v ol v il t as ffh srd t oeh t dap ,t dae t ehrl prpgram or erase address valid t a(ce) t a(oe) read status register write read array command t ps v ih v il v ih v il t wph t wps v hh t blh t bls t cep t ceph f-ce# f-oe# f-we# f-ry/by# address data f-rp# f-wp1#, wp2# note, (1) block rrase: din1=20h, din2=d0h ( t dae : duration of block erase) (2) page buffer write to flash : din1=0eh, din2=d0h ( t dap : duration of program) (3) lock bit program / confirm: din1=77h, din2=d0h ( t dap : duration of program) (4) erase all unlocked blocks / confirm : din1=a7h, din2=d0h ( t fers : duration of chip erase)
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. ac waveforms for page buffer write operation (we# control) 12 din v ih v il v ih v il v ih v il f-ce# f-we# v ih v il t as t cs t wp t ch t wph t ah t ds t dh address valid data address ac waveforms for page buffer write (ce# control) din v ih v il v ih v il v ih v il f-ce# f-we# v ih v il t as t ws t cep t wh t ceph t ah t ds t dh address valid data address full status check procedure sr.5 = 0 ? sr.4 = 0 ? sr.4 =1 and sr.5 =1 ? sucessful (block erase, program) yes yes no status register read command sequence error no block erase error no program error (block) sr.3 = 0 ? yes no program error ( page, lock bit)
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 13 write 77h write d0h block address sr.4 = 0 ? yes yes no no start lock bit program error sr.7 = 1 ? lock bit program flow chart rp#=wp#(1,2)=v ih,or rp#=v ihh lock bit program successful rp#=v ih , wp#(1,2)=v il block erase flow chart start write 20h write d0h block address full status check if desired yes sr.7 = 1 ? write b0h ? yes no suspend loop write d0h yes no status register read block erase completed
mitsubishi lsis 16777216-bit (2 m x 8-bit) cmos 3.3v-only flash memory M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 14 start write b0h operartion resumed sr.6 =1? yes no write ffh read arry data done reading ? no yes write d0h suspend resume status register read sr.7 = 1? yes no program / erase completed suspend / resume flow chart program flow chart (page buffer write to flash flow) start write dbh, x, x write address n, data n write b0h ? full status check if desired program completed yes yes no no suspend loop yes write d0h no yes n = 0 n = n+1 n = ffh ? yes no sr.7 = 1 ? write e0h, ffh, 00h write 5fh, x, x write 0eh write address, d0h start load page buffer sequential load page buffer page buffer write to flash and sr.7 = 1 ? sr.6 = 1 note; block erase /confirm command(20h/doh) and lock bit pro gram /confirm command is not allowed as two-dummy cycle s after start page buffer load command and end page buffer load command is written.
mitsubishi lsis 2097152-bit (256k x 8-bit) cmos static ram M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 15 function function table mode dq icc s-ce1# s-we# s-oe# non selection write read d in d out h x x l l l l h h x l h s-ce2 l x h x h h x x non selection high impedance high impedance high impedance standby active active active standby 2. sram the sram of the m6mft/b16s2tp is the same chip with m5m5v208 and its operation mode is determined by a combination of the device control inputs s-ce1#, s-ce2, s-we# and s-oe#. each mode is summarized in the function table. a write cycle is executed whenever the low level s-we# overlaps with the low level s-ce1# and the high level s-ce2. the address must be set up before the write cycle and must be stable during the entire cycle. the data is latched into a cell on the trailing edge of s-we#,s-ce1# or s-ce2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. the output enable input s-oe# directly controls the output stage. setting the s-oe# at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. a read cycle is executed by setting s-we# at a high level and s-oe# at a low level while s-ce1# and s-ce2 are in an active state(s-ce1#=l,s-ce2=h). when setting s-ce1# at a high level or s-ce2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high- impedance state, allowing or-tie with other chips and memory expansion by s-ce1# and s-ce2. the power supply current is reduced as low as the stand-by current which is specified as icc3 or icc4, and the memory data can be held at +2v power supply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode.
mitsubishi lsis 2097152-bit (256k x 8-bit) cmos static ram M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 2) s-ce1# 3 vcc-0.2v, 1) s-ce2 0.2v , other inputs = 0 ~ vcc s-ce2 3 vcc-0.2v other inputs = 0 ~ vcc 16 absolute maximum ratings capacitance ( ta = -20 ~ 85?, vcc = 2.7v ~ 3.6v, unless otherwise noted ) symbol parameter test conditions pf pf unit max 7 9 typ min limits v i =gnd, v i =25mvrms, f=1mhz v o =gnd,v o =25mvrms, f=1mhz input capacitance output capacitance c i c o symbol parameter v v v limits test conditions unit v ? ma ? ? ma v active supply current (mos level input) icc 1 icc 2 icc 4 v ih high-level input voltage v il low-level input voltage i o icc 3 v oh1 i oh = ?.5ma v oh2 i oh = ?.05ma v ol low-level output voltage i ol =2ma i i input current v i =0 ~ vcc s-ce1#=vih or s-ce2=v il or s-oe#=v ih v i/o =0 ~ vcc vcc +0.3v 0.6 2.0 ?.3 2.4 0.4 ? vcc -0.5v ? max typ min supply voltage (sram) inout voltage output voltage power dissipation operating temperature storage temperature v v v mw ? ? conditions with respect to gnd ta=25? 700 -20 ~ 85 ?65 ~150 ratings s-vcc v i v o p d t opr t stg ?0.3 * ~4.6 ?0.3 * ~ vcc + 0.5 0 ~ vcc (max 4.6) s-ce1# = v ih or s-ce2 = v il , other inputs = 0 ~ vcc s-ce1#=v il , s-ce2=v ih other inputs = v ih or v il output-open(duty 100%) symbol parameter unit dc electrical characterisrics (ta=-20~85?, vcc=2.7v~3.6v, unless otherwise noted) high-level output voltage1 * -3.0v in case of ac (pulse width 30ns) output current in off-state * -3.0v in case of ac (pulse width 30ns) 1mhz 5mhz 10mhz ma 0.33 25 20 - 13 10 - 5 3 - 27 22 - 15 12 - 5 3 - 40 - 5 - 2 0.3 - - - - - s-ce1# 0.2v , s-ce2 3 s-v cc -0.2v other inputs 0.2v or 3 s-v cc -0.2v output-open(duty 100%) 1mhz 5mhz 10mhz +25? -20~+40? -20~+85? high-level output voltage2 active supply current (ttl level input) stand-by current stand-by current note 1: direction for current flowing into an ic is positive (no mark). 2: typical value is vcc = 3v, ta = 25? 3: the value of common pins to flash memory is the sum of flash memory and sram.
mitsubishi lsis 2097152-bit (256k x 8-bit) cmos static ram M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 17 (2) read cycle (3) write cycle symbol parameter t cr read cycle time address access time unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns limits t a (ce1) t a (ce2) t a (oe) t dis (ce1) t dis (ce2) t dis (oe) t en (ce1) t en (ce2) t en (oe) t v (a) t a (a) chip select1 access time chip select2 access time output enable access time max min 110 110 110 55 40 40 40 110 10 10 5 10 40 40 110 85 0 100 100 100 45 0 0 5 5 t cw t w (we) t su (a) t su (a-wh) t su (ce1) t su (ce2) t su (d) t h (d) t rec (we) t dis (we) t dis (oe) t en (we) t en (oe) output disable time after s-ce1# high output disable time after s-ce2 low output disable time after s-oe# high output enable time after s-ce1# low data valid time after address output enable time after s-oe# low output enable time after s-ce2 high write cycle time write pulse width address setup time address setup time with respect to s-we# chip select1 setup time chip select2 setup time data setup time data hold time write recovery time output enable time from s-oe# low output disable time from s-we# low output disable time from s-oeh# hig output enable time from s-we# high ac electrical characteristics (ta=-20 ~ 85?, vcc=2.7v ~ 3.6v, unless otherwise noted) (1) measurement conditions v cc 2.7v ~ 3.6v input pulse level v ih =2.2v, v il =0.4v input rise and fall time 5ns reference level v oh =v ol =1.5v output loads fig.1,c l = 30pf c l = 5pf (for t en ,t dis ) transition is measured 500mv from steady state voltage. (for t en ,t dis ) ................................. ............... ..... ................... including scope and jig 1ttl c l dq fig.1 output load symbol parameter unit limits max min
mitsubishi lsis 2097152-bit (256k x 8-bit) cmos static ram M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. t en (we) 18 read cycle write cycle (we# control mode)) (4) timing diagrams data valid (note 3) (note 3) t a (a) t a (ce1) t v (a) t a (ce2) t en (ce2) t dis (ce1) t dis (ce2) t a (oe) t en (oe) t dis (oe) (note 3) (note 3) (note 3) (note 3) t cr t h (d) t su (d) dq 0-7 s-ce1# t su (ce1) s-ce2 s-oe# t su (ce2) t su (a-wh) t en (oe) t dis (oe) s-we# t w (we) t rec (we) t su (a) t dis (we) t cw t en (ce1) s-we# = "h" level a 0~17 dq 0-7 s-ce1# s-ce2 s-oe# a 0~17 data in stable (note 3) (note 3) (note 3) (note 3)
mitsubishi lsis 2097152-bit (256k x 8-bit) cmos static ram M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 19 write cycle (ce1# control mode) write cycle (ce2 control mode) t su (ce1) (note 3) (note 3) t rec (we) t h (d) t cw (note 5) t su (a) (note 4) t su (d) t h (d) t cw (note 5) t su (ce2) t rec (we) t su (a) (note 4) t su (d) data in stable data in stable dq 0-7 s-ce1# s-ce2 s-we# a 0~17 dq 0-7 s-ce1# s-ce2 s-we# a 0~17 (note 3) (note 3) (note 3) (note 3) (?? 3) (note 3) note 3: hatching indicates the state is "don't care". 4: writing is executed while s-ce2 high overlaps s-ce1# and s-we# low. 5: when the falling edge of s-we# is simultaneously or prior to the falling edge of s-ce1# or rising edge of s-ce2, the outputs are maintained in the high impedance state. 6: don't apply inverted phase signal externally when dq pin is output mode.
mitsubishi lsis 2097152-bit (256k x 8-bit) cmos static ram M6MF16S2AVP may.1998 , rev.1.2 preliminary notice : this is not a final specification. some parametric limits are subject to change. 0.2v t rec (pd) s-ce2 0.2v 20 (3) power down characteristics ce1# control mode ce2 control mode (1) electrial characteristics (ta=-20 ~ 85?, unless otherwise noted) power down set up time power down recovery time (2) timing requirements (ta=-20 ~ 85?, unless otherwise noted) t su (pd) t rec (pd) symbol paramwter ns test conditions 0 5 ms t su (pd) 0.2v 2.2v t su (pd) 2.2v t rec (pd) s-ce1# 3 vcc - 0.2v s-vcc s-ce1# s-vcc s-ce2 symbol parameter v v max typ limits min test conditions unit ? v 2 0.2 0.3 30 vcc (pd) v i (ce1#) v i (ce2) icc (pd) power down supply voltage chip select input s-ce1# chip select input s-ce2 power down supply current s-vcc = 3v 2.0 power down characteristics max typ min limits unit 2) s-ce1# 3 vcc-0.2v,s-ce2 3 vcc-0.2v 1) s-ce2 0.2v, other input = 0 ~ vcc other inputs = 0 ~ vcc 2.7v 2.7v 2.7v 2.7v +25? -20~+40? -20~+85? 3 1

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